E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods

E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods” by Eshan Singh, Clark Barrett, and Subhasish Mitra. In Proceedings of the 29^th International Conference on Computer Aided Verification (CAV '17), (Rupak Majumdar and Viktor Kuncak, eds.), July 2017, pp. 104-125. Heidelberg, Germany.

Abstract

During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation. Our results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours (9 hours on average) we can automatically narrow the location of the bug to (the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on average for a design with   1 Million flip-flops) and also obtain the corresponding bug trace. The area impact of E-QED is  2.5%. In contrast, determining this same information might take weeks (or even months) of mostly manual work using traditional approaches.

BibTeX entry:

@inproceedings{SBM17,
   author = {Eshan Singh and Clark Barrett and Subhasish Mitra},
   editor = {Rupak Majumdar and Viktor Kuncak},
   title = {{E-QED}: Electrical Bug Localization During Post-Silicon
	Validation Enabled by Quick Error Detection and Formal Methods},
   booktitle = {Proceedings of the {\it 29^{th}} International Conference
	on Computer Aided Verification (CAV '17)},
   series = {Lecture Notes in Computer Science},
   volume = {10426},
   number = {1},
   pages = {104--125},
   publisher = {Springer},
   month = jul,
   year = {2017},
   note = {Heidelberg, Germany},
   url = {http://theory.stanford.edu/~barrett/pubs/SBM17.pdf}
}

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