“E-QED: Electrical Bug Localization during Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods” by Eshan Singh, Clark Barrett, and Subhasish Mitra. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, IEEE. under review.
Keywords: Post-silicon validatoin, Electrical bugs, Bug localization, formal methods, Bounded model checking, Quick Error Detection
BibTeX entry:
@article{SBM20, author = {Eshan Singh and Clark Barrett and Subhasish Mitra}, title = {{E-QED}: Electrical Bug Localization during Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher = {IEEE}, year = {2021}, note = {under review} }
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