The first paragraph of the quoted argument argues that two overlapping writes of the variable turn cannot leave any other value in the turn register than could have originated from performing these writes in some non-overlapping order. This argument is correct. It concludes from this that one can just as well assume that these writes did not overlap. That conclusion is incorrect. If only that conclusion would stand, everything written in the second paragraph of the quoted argument, and thereby the conclusion that Peterson's protocol remains correct under overlapping reads and writes, would be justified.
The possibility that the first paragraph fails to consider is that a write $\ell_3$ of the value $B$ in the Boolean register turn overlaps with both another write $m_3$ of the value $A$ and with a read $m_4$. Although this implies that the write $\ell_3$ ends strictly later than the write $m_3$, the assumption that the register is safe, made in Section 20, leaves open the possibility that the value $A$, written by $m_3$, ends up in the register, rather than the value $B$ written by $\ell_3$. At the same time, since the read action $m_4$ overlaps with the write $\ell_3$, it might read the value $B$.
This scenario is not possible when $\ell_3$ and $m_3$ would not overlap. For if the value $A$ written by $m_3$ ends up in the register after both $\ell_3$ and $m_3$ have concluded, then that would also be the value read by $m_4$.
Simply assume that a write (of $A$) to a Boolean register is implemented by first writing the opposite ($B$) and subsequently turning the current register value into its complement. This may seem a weird implementation, but in real hardware many things happen that even logicians may find weird. The definition of a safe register was chosen explicitly to allow any implementation, even a weird one.
Now the above scenario could occur by (a) $m_3$ writing $B$, (b) $\ell_3$ writing $A$, (c) $m_3$ complementing $A$ into $B$, and (d) $\ell_3$ complementing $B$ into $A$, in that order. The read $m_4$ occurs between (c) and (d).