Creating an Agile Hardware Design Flow

“Creating an Agile Hardware Design Flow” by R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan, T. Hofstee, M. Horowitz, D. Huff, F. Kjolstad, T. Kong, Q. Liu, M. Mann, J. Melchert, A. Nayak, A. Niemetz, G. Nyengele, P. Raina, S. Richardson, R. Setaluri, J. Setter, K. Sreedhar, M. Strange, J. Thomas, C. Torng, L. Truong, N. Tsiskaridze, and K. Zhang. In Proceedings of the 57^th Design Automation Conference (DAC '20), July 2020.

Abstract

Although an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. This work addresses this question while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA). As our under-standing of the application grows, the CGRA design evolves, and we have developed a suite of tools that tune application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our continued need to update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators that not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain.

BibTeX entry:

@inproceedings{BBB+20,
   author = {R. Bahr and C. Barrett and N. Bhagdikar and A. Carsello and
	R. Daly and C. Donovick and D. Durst and K. Fatahalian and K. Feng
	and P. Hanrahan and T. Hofstee and M. Horowitz and D. Huff and F.
	Kjolstad and T. Kong and Q. Liu and M. Mann and J. Melchert and A.
	Nayak and A. Niemetz and G. Nyengele and P. Raina and S.
	Richardson and R. Setaluri and J. Setter and K. Sreedhar and M.
	Strange and J. Thomas and C. Torng and L. Truong and N.
	Tsiskaridze and K. Zhang},
   title = {Creating an Agile Hardware Design Flow},
   booktitle = {Proceedings of the {\it 57^{th}} Design Automation
	Conference (DAC '20)},
   publisher = {Association for Computing Machinery},
   month = jul,
   year = {2020},
   doi = {10.1109/DAC18072.2020.9218553},
   url = {http://theory.stanford.edu/~barrett/pubs/BBB+20.pdf}
}

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