“Post-silicon validation and debug using symbolic quick error detection” by Subhasish Mitra, Clark Barrett, David Lin, and Eshan Singh. Jan. 2020. Patent No. 10528448.
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting “change detectors” during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection.
BibTeX entry:
@misc{MBLS20,
author = {Subhasish Mitra and Clark Barrett and David Lin and Eshan Singh},
title = {Post-silicon validation and debug using symbolic quick error
detection},
number = {10528448},
month = jan,
year = {2020},
note = {Patent No. 10528448},
url = {http://www.freepatentsonline.com/10528448.html}
}
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