“APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis” by Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Ritvik Sharma, Clark Barrett, Mark A. Horowitz, Pat Hanrahan, and Priyanka Raina. In Proceedings of the 28^th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Volume 3, (New York, NY, USA), Mar. 2023, pp. 33-45. Vancouver, BC, Canada.
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy-efficiency of an application running on the CGRA. This paper presents APEX, an automated approach for generating specialized PE architectures for an application or an application domain. APEX first analyzes application domain benchmarks using frequent subgraph mining to extract commonly occurring computational subgraphs. APEX then generates specialized PEs by merging subgraphs using a datapath graph merging algorithm. The merged datapath graphs are translated into a PE specification from which we automatically generate the PE hardware description in Verilog along with a compiler that maps applications to the PE. The PE hardware and compiler are inserted into a flexible CGRA generation and compilation toolchain that allows for agile evaluation of CGRAs. We evaluate APEX for two domains, machine learning and image processing. For image processing applications, our automatically generated CGRAs with specialized PEs achieve from 5% to 30% less area and from 22% to 46% less energy compared to a general-purpose CGRA. For machine learning applications, our automatically generated CGRAs consume 16% to 59% less energy and 22% to 39% less area than a general-purpose CGRA. This work paves the way for creation of application domain-driven design-space exploration frameworks that automatically generate efficient programmable accelerators, with a much lower design effort for both hardware and compiler generation.
Keywords: subgraph, reconfigurable accelerators, processing elements, hardware-software co-design, graph analysis, domain-specific accelerators, design space exploration, CGRA
BibTeX entry:
@inproceedings{MFD+23,
author = {Jackson Melchert and Kathleen Feng and Caleb Donovick and
Ross Daly and Ritvik Sharma and Clark Barrett and Mark A. Horowitz
and Pat Hanrahan and Priyanka Raina},
title = {{APEX}: A Framework for Automated Processing Element Design
Space Exploration using Frequent Subgraph Analysis},
booktitle = {Proceedings of the {\it 28^{th}} {ACM} International
Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS), Volume 3},
series = {ASPLOS 2023},
pages = {33--45},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
month = mar,
year = {2023},
isbn = {9781450399180},
doi = {10.1145/3582016.3582070},
note = {Vancouver, BC, Canada},
url = {https://doi.org/10.1145/3582016.3582070}
}
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