Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions

“Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions” by Eshan Singh, David Lin, Clark Barrett, and Subhasish Mitra. IEEE Design & Test, vol. 33, no. 6, Dec. 2016, pp. 55-62, IEEE.

Abstract

Reducing the error detection latency is critical for improving the design visibility while searching for design errors. This article uses a FAQ format to discuss the key points of the symbolic QED method that can be applied during both pre-silicon and post-silicon validation.

Keywords: Computer bugs, Error detection, Silicon, Measurement, Integrated circuit modeling, Symbolic Quick Error Detection, Debug, Post-Silicon Validation, Pre-silicon verification

BibTeX entry:

@article{SLB+16,
   author = {Eshan Singh and David Lin and Clark Barrett and Subhasish Mitra},
   title = {Symbolic Quick Error Detection for Pre-Silicon and
	Post-Silicon Validation: Frequently Asked Questions},
   journal = {IEEE Design & Test},
   volume = {33},
   number = {6},
   pages = {55--62},
   publisher = {IEEE},
   month = dec,
   year = {2016},
   issn = {2168-2356},
   doi = {10.1109/MDAT.2016.2590987},
   url = {http://theory.stanford.edu/~barrett/pubs/SLB+16.pdf}
}

(This webpage was created with bibtex2web.)